PCA9634D,118【PDF 27/38 页】IC LED DRIVER RGBA 20-SOIC

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NXP Semiconductors

PCA9634

8-bit Fm+ I 2 C-bus LED driver

Table 17. Static characteristics …continued

V DD = 2.3 V to 5.5 V; V SS = 0 V; T amb = ? 40 ° C to +85 ° C; unless otherwise speci?ed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Address inputs

V IL

LOW-level input voltage

? 0.5

-

+0.3V DD V

V IH

I LI

C i

HIGH-level input voltage

input leakage current

input capacitance

0.7V DD

? 1

-

-

-

3.7

5.5

+1

5

V

μ A

pF

[1]

[2]

V DD must be lowered to 0.2 V in order to reset part.

Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.

13. Dynamic characteristics

Table 18.

Dynamic characteristics

Symbol Parameter

Conditions

Standard-mode

I 2 C-bus

Fast-mode

I 2 C-bus

Fast-mode Plus Unit

I 2 C-bus

Min

Max

Min

Max

Min

Max

f SCL

t BUF

SCL clock frequency

bus free time between a

[1]

0

4.7

100

-

0

1.3

400

-

0

0.5

1000

-

kHz

μ s

STOP and START condition

t HD;STA

hold time (repeated) START

4.0

-

0.6

-

0.26

-

μ s

condition

t SU;STA

set-up time for a repeated

4.7

-

0.6

-

0.26

-

μ s

START condition

t SU;STO

set-up time for STOP

4.0

-

0.6

-

0.26

-

μ s

condition

t HD;DAT

data hold time

0

-

0

-

0

-

ns

t VD;ACK

t VD;DAT

t SU;DAT

t LOW

t HIGH

data valid acknowledge time

data valid time

data set-up time

LOW period of the SCL clock

HIGH period of the SCL

[2]

[3]

0.3

0.3

250

4.7

4.0

3.45

3.45

-

-

-

0.1

0.1

100

1.3

0.6

0.9

0.9

-

-

-

0.05

0.05

50

0.5

0.26

0.45

0.45

-

-

-

μ s

μ s

ns

μ s

μ s

clock

t f

fall time of both SDA and

[4][5]

-

300

20 + 0.1C b [6]

300

-

120

ns

SCL signals

t r

rise time of both SDA and

-

1000

20 + 0.1C b [6]

300

-

120

ns

SCL signals

t SP

pulse width of spikes that

[7]

-

50

-

50

-

50

ns

must be suppressed by the

input ?lter

[1]

[2]

[3]

[4]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V IL of the SCL signal) in order to

bridge the unde?ned region of SCL’s falling edge.

PCA9634_6

? NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 12 September 2008

27 of 38

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